Difference between DDR, DDR2 and DDR3 RAM

Difference between DDR, DDR2 and DDR3 RAM

DDR (DDR1), DDR2 and DDR3 are different types of SDRAM that are used in computers. DDR2 provides a faster transfer rate, bus clock and is more power-friendly compared to DDR1. DDR3 is an advanced version of the same technology. It enables faster bus speeds and higher peak throughput than earlier memory technologies. All three memories differ in various contexts like technical and physical specifications.

Comparison between DDR, DDR2 and DDR3 RAM:

	DDR RAM	DDR2 RAM	DDR3 RAM
Full Form	Double Data Rate 1 Random Access Memory	Double Data Rate 2 Random Access Memory	Double Data Rate 3 Random Access Memory
Maximum Theoretical Transfer Rate (MB/s)	DDR200 -1600 DDR266 - 2133 DDR333 - 2666 DDR400 - 3200	DDR2(400) - 3200 DDR2(533) –  4266 DDR2(667) - 5333 DDR2 (800) – 6400 DDR2(1066) - 8533	DDR3(800) - 6400 DDR3(1066) – 8500 DDR3(1333) - 10666 DDR3(1600) – 12800
Bus Speed (MHz)	DDR200 -100 DDR266 - 133 DDR333 - 166 DDR400 - 200	DDR2(400) - 200 DDR2(533) –  266 DDR2(667) - 333 DDR2 (800) – 400	DDR3(800) - 400 DDR3(1066) – 533 DDR3(1333) - 667 DDR3(1600) – 800
Voltage	Operates at comparatively highest voltage.	Lower in comparison to DDR and higher in comparison to DDR3.	Operates at comparatively lowest voltage.
Typical Latency	3	5	7
Number of Pins	184	240	240
Features	Prefetching – based on a 2n-prefetch architecture. Double transition clocking – provides twice the bandwidth of SDRAM without the need of increasing the clock frequency. Stub-Series Terminated Logic_2 (SSTL_2) low-voltage signaling technology – It uses e 2.5-V signaling specification SSTL_2. Strobe-based data bus – Used for locating the data in a more accurate manner.	Connector of 240 pins Faster clocks 1.8-V operation and signaling A simplified command set	An eight bit prefetch buffer stores more data than the 4-bit buffer of DDR2. Fly-by topology for the commands, addresses, control signals, and clock to improve the integrity of signals. 1.5-V signaling reduces power consumption from the 1.8- V signaling for DDR2. A thermal sensor integrated on the DIMM module signals the chipset to throttle memory traffic.
Packaging	Thin small-outline package	Ball Grid Array	Ball Grid Array
Succeeded by	DDR2	DDR3	DDR4
Data Strobes	Single-ended	Single-ended or differential	Differential only
Modules	184-pin DIMM unbuffered registered; 200-pin SODIMM; 172-pin MicroDIMM	240-pin DIMM unbuffered registered; 200-pin SODIMM; 214-pin MicroDIMM	240-pin DIMM (same size as DDR2 but are electrically incompatible with DDR2 DIMMs and have a different key notch location). DDR3 SO-DIMMs have 204 pins.
Prefetch Buffer (bits)	2	4	8

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